Low voltage trigger silicon controlled rectifiers (LVTSCR) are often used as electrostatic discharge (ESD) protection devices because of their high performance and small size. LVTSCRs do have a number of drawbacks, however. For instance, they are prone to latch-up either during testing or caused by noise on the power bus of the circuit to be protected.
FIG. 1 shows the IV characteristics for a typical LVTSCR. As is known in the art of ESD protection devices, the LVTSCR has a trigger point 2 at which the snapback occurs. Thereafter, the LVTSCR operates in a holding region 4 to shunt the ESD current (e.g. to ground). As can be seen in FIG. 1, the holding region of a typical LVTSCR may be located below the supply voltage level (Vdd) of the circuit to be protected. Because of this, if the LVTSCR is triggered by a noise pulse during normal operation of the circuit, latch-up may occur, in which the LVTSCR does not deactivate. Latch-up generally leads to device failure.
There are two general approaches to addressing this problem, which are illustrated in FIGS. 2A and 2B. A first approach, shown in FIG. 2A, is to attempt to increase the holding voltage of the LVTSCR so that the holding region is located above the supply voltage (Vdd). In this way, if the LVTSCR is triggered by a noise pulse, it may subsequently deactivate. Another approach is to attempt to increase the trigger current of the LVTSCR as shown in FIG. 2B, so as to reduce the tendency for the LVTSCR to be triggered by a noise pulse.